Gene Frantz
TI Principal Fellow and Business Development Manager, DSP

Over the last several months, I’ve been working with some of my colleagues to articulate the future of IC architectures. One of the things that is clear, we are no longer in a world where Moore’s law can and should always apply. Here I’m trying to outline why I think that is and look forward to hearing what your thoughts are on the topic.

When following the progression of modern processor architectures, it is possible to see where we may have lost our way. The introduction of the first microprocessor allowed us to process very simple signals in real time. During this time, the array processor and mini-computer were considered the state-of-the-art tools for signal processing and premier choice in the research community. As researchers discovered and developed new signal processing concepts and algorithms, another community of technologists were already on the path to creating the first DSP device. Approximately 20 years after the invention of the transistor, the first commercially available DSPs appeared on the market and dramatically changed the future of the world.

Early work in DSP algorithm implementation focused on reducing the number of multiplications since multiplies were expansive and slow when implemented in hardware. The primary breakthrough of widespread DSP adoption was the addition of a specialized hardware multiplier to the microprocessor. This innovation changed the focus of digital signal processing from reducing the number of multiplies required by an algorithm to instead, optimizing the numbers of necessary multiplies and additions.

Another major facet of the fast evolving DSP architecture was the use Harvard architecture (two busses – one for program memory and one for data memory) rather than Von Neuman architecture (a single bus with program and data sharing the same memory space). To better suit the needs of mathematically intense processors, the two busses of the Harvard architecture were modified to support both program and data memory allowing both busses to feed the multiplier.

To take advantage of the accelerated multiplication capabilities, new instructions were created to bring together the necessary operations to perform a multiply in a single instruction cycle. Later, the accumulate operation was added to create the familiar MAC function.

Further improvements to the DSP architecture followed. Combining the best of both the Harvard and Von Neuman architectures resulted in a multiple bus Von Neuman-style architecture. As IC performance increased, the concept of the Very Long Instruction Word (VLIW) was introduced allowing parallel processing to meet real-time constraints.

Modern architectures continue to press the limits of performance and efficiency through innovations such as deep pipelines, extensive branch prediction technology and advanced instruction sets. These innovations, in turn create new challenges even as they overcome previous limitations, which I plan to discuss in several future blogs.